The present invention relates to a CMOS logic circuit which comprises CMOSFETs and, more particularly, to a high-speed arrangement of a multi-input logic circuit.
In a conventional CMOS logic circuit, a drive circuit comprises N-channel MOSFETs, and a load circuit comprises P-channel MOSFETs. The N- and P-channel MOSFETs are used in the drive and load circuits in a complementary manner. FIG. 1 is a circuit diagram of an N-input NAND gate in a typical CMOS logic circuit. The load circuit 11 comprises P-channel MOSFETs QP1, QP2, QP3 . . . which are connected in parallel with each other, and the drive circuit 12 comprises N-channel MOSFETs QN1, QN2, QN3 . . . which are connected in series with each other. The common node of one terminal of each of the MOSFETs QP1, QP2, QP3 . . . is connected to a voltage source 13 for supplying an operating voltage Vcc. The common node of the other terminal of each of the MOSFETs QP1, QP2, QP3 . . . is connected to one terminal of the MOSFET QN1 and to an output terminal 14. The other terminal of the MOSFET QN1 is connected to a ground through the MOSFETs QN2, QN3 . . . The gates of the MOSFETs QP1 and QN1, QP2 and QN2, QP3 and QN3 . . . , respectively, are commonly connected, and the common gate nodes are connected to input terminals 15a, 15b, 15c which receive input signals A, B, C . . . , respectively.
The operation of the NAND gate described above will be described hereinafter. Assume that "L" level is defined as the ground potential, and that "H" level is defined as the operating potential Vcc. When the input signals A, B, C . . . are all set at the "L" level, the MOSFETs QP1, QP2, QP3 . . . are turned on, and the MOSFETs QN1, QN2, QN3 . . . are turned off. Therefore, the output signal is set at the "H" level. When at least one of the input signals A, B, C . . . is set at the "L" level, the corresponding MOSFET QP1, QP2, QP3 . . . is turned on, and the gate of the N-channel MOSFET (in the drive circuit 12) which happens to be connected to the gate thereof is turned off. Therefore, the output signal is set at the "H" level. On the other hand, when the input signals A, B, C . . . are all set at the "H" level, all the MOSFETs QP1, QP2, QP3 . . . are turned off, and all the MOSFETs QN1, QN2, QN3 . . . are turned on. Thus, the output signal is set at the "L" level. In this manner, a NAND output A.multidot.B.multidot.C . . . of the input signals A, B, C . . . appears at the output terminal 14.
However, when the multi-input logic circuit is constituted by a CMOS static circuit, and the number of input signals is increased, the delay time of the output increases in proportion to the power of the number N of the input signals. As a result, the operating speed is lowered, resulting in inconvenience. This is because when the N-channel MOSFETs are connected in series with each other in the drive circuit of the NAND gate, the output voltage is shunted as a drain-source voltage of each of the N-channel MOSFETs QN1, QN2, QN3 . . . , the gate-source voltage of each of the MOSFETs drops, and hence the current flowing through the drive circuit decreases. In addition, when the number of series-connected MOSFETs is increased, the source voltages of the MOSFETs also increase due to the voltage drop, so that the source-substrate path is reversely biased. As a result, the effective threshold voltage of the MOSFET increases due to the back-gate effect, and the current flowing from the drain to the source of each MOSFET decreases, thereby decreasing the operating speed.
In order to solve the problems described above, the channel width of each of the MOSFETs QN1, QN2, QN3 . . . in the drive circuit can be increased. However, when the channel width is increased, the channel pattern area is increased, thereby increasing the parasitic capacitance, the charge/discharge current, and hence power consumption.
In the arrangement wherein the drive circuit has MOSFETs connected in series with each other, the priority order of input signals must be considered, since the operating speed depends on the last input signal. When the input signals are sequentially supplied in a predetermined order, they must be supplied from the MOSFET QN1 connected to the output terminal 14 to the MOSFET connected to the ground terminal through QN2, QN3 . . . , respectively.